1. Technical Field
Methods of manufacturing flash memory cells are disclosed, and more particularly methods of manufacturing flash memory cells that prevent generation of etching damage at the sidewall of a stack gate when an etching process for forming a control gate and a floating gate is performed.
2. Description of the Related Art
Generally, a flash memory cell has a structure in which a tunnel oxide film, a floating gate consisting of a first polysilicon layer, a dielectric film, a control gate made of a second polysilicon layer, and a tungsten silicide layer are stacked. At this time, source and drain are formed at both sides of the tunnel oxide film.
The flash memory cell constructed above is formed by first patterning the tungsten silicide layer, the second polysilicon layer and the dielectric film by means of an etching process and then patterning the first polysilicon layer and the tunnel oxide film by means of a self-aligned etch (SAE) process.
At this time, during the process of patterning the first polysilicon layer and the tunnel oxide film using the self-aligned etch (SAE) process, etching damage is generated at the sidewall of the tungsten silicide layer due to an etch profile of the dielectric film, the second polysilicon layer and the tungsten silicide layer, being an upper layer, and Cl2 being an etch gas.
A conventional method of manufacturing a flash memory cell will be below described by reference to the drawings.
FIG. 1 is a layout diagram of a conventional flash memory cell, FIG. 2A through FIG. 2D are cross-sectional views of the flash memory cell for explaining a method of manufacturing the flash memory cell with the layout in FIG. 1 taken along lines X-X′, and FIG. 3A through FIG. 3E are cross-sectional views of the flash memory cell for explaining a method of manufacturing the flash memory cell with the layout in FIG. 1 taken along lines Y-Y′.
Referring now to FIG. 1, FIG. 2A and FIG. 3A, a device isolation film 12 is formed at a device isolation region of a semiconductor substrate 11. A tunnel oxide film 13 is then formed on the surface of the semiconductor substrate 11 in which the device isolation film 12 is not formed. Next, a first polysilicon layer 14 for forming a floating gate is formed on the entire surfaces.
By reference to FIG. 1 and FIG. 2B, the first polysilicon layer 14 on the device isolation film 12 is removed by an etching process. Thus, the first polysilicon layer 14 is isolated electrically.
Referring now to FIG. 1, FIG. 2C and FIG. 3B, a dielectric film 15, a second polysilicon layer 16 for a control gate, a tungsten silicide layer 17 and an anti-reflection film 18 are sequentially formed on the entire surfaces.
At this time, the tungsten silicide layer 17 is formed in order to reduce the contact resistance of the control gate. The anti-reflection film 18 made of a nitride material is formed in order to improve a patterning characteristic in a subsequent etching process.
Next, a control gate mask pattern 19 made of a photoresist or a hard mask is formed on the anti-reflection film 18.
Referring now to FIG. 1 and FIG. 3C, the anti-reflection film 18, the tungsten silicide layer 17, the second polysilicon layer 16 and the dielectric film 15, at the regions that are exposed by the control gate mask pattern 19, are removed by the etching process. Therefore, a control gate consisting of the second polysilicon layer 16 and the tungsten silicide layer 17 is formed. The first polysilicon layer 14 is also exposed at the region for which the etching process is performed.
After the control gate is formed by the etching process, a cleaning process is performed using BOE ranging from 300:1 through 100:1 in order to remove a particle of oxide series and polymer which are generated when the dry etching process for the control gate is performed.
Referring now to FIG. 1, FIG. 2D and FIG. 3D, the first polysilicon layer 14 and the tunnel oxide film 13 are patterned by the self-aligned etching process. The control gate mask pattern is then removed. Therefore, a floating gate consisting of the first polysilicon layer 14 is formed.
At this time, the self-aligned etching process for forming the floating gate includes performing a dry etching process using a gas mixture of Cl2/O2. In case that the gas mixture of Cl2/O2 is used, the etch selective ratio of the polysilicon layer to the tungsten silicide layer is 1.2:1 through 1.5:1. Therefore, the dry etching process is performed in a state that the etch selective ratio of the polysilicon layer to the tungsten silicide layer is not sufficiently obtained. Further, as the dry etching process is performed in a state that polymer or particle is removed and the sidewall of the tungsten silicide layer 17 is exposed by the cleaning process, etching damage 100 is generated at the sidewall of the tungsten silicide layer 17 depending on an atmosphere of an etch chamber or an etch condition.
Referring now to FIG. 1 and FIG. 3E, a source and a drain 20a and 20b are formed at both sides of the first polysilicon layer 14 by means of an ion implantation process. The ion implantation process includes performing a self-aligned ion implantation process using the nitride film 18 as an ion implantation mask.
At this time, all the sources 20a in a cell that share the control gate are connected by implanting an impurity into even a region from which the device isolation film 12 is removed after removing a given region of the device isolation film 12. Thereby, the source 20a is formed to have a shape of a common source line.
With the above processes, a flash memory cell consisting of the floating gate, the control gate, the source and the drain is manufactured.
As described above, in a process of manufacturing the flash memory cell, the dry etching process and cleaning process are performed twice in order to form the control gate and the floating gate. At this time, etching damage is generated at the sidewall of the tungsten silicide layer that is exposed during the dry etching process for forming the floating gate. Due to this, the sheet resistance Rs of the control gate is increased and an electrical characteristic of a device is thus degraded.
FIG. 4A and FIG. 4B show cross-sectional SEM photographs illustrating a state that etching damage is generated at the sidewall of a tungsten silicide layer. In particular, FIG. 4A shows a cross-sectional SEM photography when the control gate mask pattern is formed using the photoresist and FIG. 4B shows a cross-sectional SEM photography when the control gate mask pattern is formed using the hard mask.
Referring now to FIG. 4A and FIG. 4B, after polymer or a particle is removed, the self-aligned etching process for forming the floating gate is performed with the sidewall of the tungsten silicide layer being exposed. Thus, it could be seen that etching damage is generated at the sidewall of the tungsten silicide layer regardless of a material forming the control gate mask pattern. This etching damage is not always generated but generated depending on an atmosphere of an etch chamber or an etch condition.
Therefore, there are problems that not only reliability of the process is degraded but also the electrical characteristic of a device is degraded.